Exemplary embodiments relate to a method of erasing a semiconductor memory device.
There is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and can retain data even without the supply of power. In order to develop high-capacity memory devices capable of storing a large amount of data, techniques for the high integration of memory cells are being developed. The nonvolatile memory device includes a memory cell array including a plurality of memory cell strings. Each of the memory cell strings includes a plurality of memory cells coupled in series.
A memory cell includes a gate and junctions formed on a semiconductor substrate on both sides of the gate. The gate has a structure in which a tunnel insulating layer, a floating gate, a dielectric layer, and a control gate are stacked over the semiconductor substrate. During a program operation, hot electrons are injected into the floating gate, and so a program is performed. During an erase operation, the electrons injected into the floating gate are discharged by means of F-N tunneling, and so erase is performed.
FIG. 1 is a cross-sectional view of a unit memory cell string of a nonvolatile memory device.
The unit memory cell string of the nonvolatile memory device includes memory cells coupled to 0th to 31st word lines WL0 to WL31, respectively, between a drain select line DSL and a source select line SSL.
In the nonvolatile memory device having the unit memory cell string structure, when a program operation is performed, a program voltage Vpgm is supplied to a selected word line, and a pass voltage Vpass is supplied to the remaining word lines.
FIG. 1 shows a case in which the 29th word line WL29 is selected and supplied with the program voltage Vpgm, for a program. The program voltage Vpgm is supplied to the 29th word line WL29, and the pass voltage Vpass is supplied to the remaining word lines.
Here, the program voltage Vpgm is supplied to not only the selected memory cell, but also other memory cells of other memory cell strings sharing the same word line, and so unselected memory cells sharing the same word line may be programmed. This phenomenon is called a program disturbance phenomenon.
In order to prevent the program disturbance phenomenon, during the time for which a program operation is performed by charging bit lines, coupled to the unselected memory cells, with a Vcc-Vth level (Vcc is a power supply voltage and Vth is the threshold voltage of a drain select transistor), the channel voltage Vch of the memory cell string is boosted so that the unselected memory cells are prevented from being programmed.
In this case, if the channel boosting level is low, F-N tunneling program disturbance may be generated. If the channel boosting level is high, program disturbance due to hot electron injection may be generated. Accordingly, a method of controlling the pass voltage Vpass supplied to the word line may be used for proper channel boosting.
Furthermore, channel boosting may be disturbed by the threshold voltage levels of memory cells adjacent to a selected memory cell. In order to address this concern, an erase area self-boosting method is used.
FIG. 2 is a diagram illustrating a state in which channel boosting is generated when voltage is supplied to a program-inhibited memory cell string in order to describe a program disturbance phenomenon generated due to an erase cell.
Referring to FIG. 2, in the memory cell string having the same structure as the memory cell string of FIG. 1, a 29th word line WL29 is selected and supplied with a program voltage Vpgm, for performing a program operation.
In order to perform channel boosting for program inhibition, a third pass voltage Vpass3 is supplied to the 25th word line WL25, and a second pass voltage Vpass2 is supplied to a 26th word line WL26. A first pass voltage Vpass1 is supplied to the remaining word lines.
Here, the first pass voltage Vpass1 is 8V, the second pass voltage Vpass2 is 5 V, and the third pass voltage Vpass3 is 3 V.
As shown in FIG. 2, first to third channels CH1 to CH3 are formed in the memory cell string because of the word line voltages.
Furthermore, the channel voltage of the second channel CH2 is boosted, and so the 29th memory cell C29 coupled to the 29th word line WL 29 may be program-inhibited.
When a program operation is performed, in the case where word line voltages are supplied as shown in FIG. 2, the program states of surrounding memory cells have a great influence on channel boosting.
For example, it is assumed that the 29th memory cell C29 is an erase cell that has not been programmed.
A third pass voltage Vpass3 is supplied to the gate (that is, the 25th word line WL25) of the 25th memory cell C25. For a normal operation, a channel voltage of the second channel CH2 can be sufficiently boosted only when the 25th memory cell C25 is turned off.
The 25th memory cell C25 is in the erase state. When the channel voltage of the second channel CH2 is raised through boosting, the 25th memory cell C25 is turned off. Accordingly, the first and second channels CH1, CH2 are separated from each other, the channel voltage of the second channel CH2 is raised, and so the 29th memory cell C29 is program-inhibited.
Here, if the 25th memory cell C25 is excessively erased at 0 V or less, the 25th memory cell C25 is not turned off, but may remain turned on during the channel boosting process.
When the 25th memory cell C25 is turned on, charge sharing is generated in the second channel CH2. If the channel voltage of the second channel CH2 is lowered by such charge sharing, a sufficient boosting effect is not obtained. In other words, the 29th memory cell C29 may be programmed.
Accordingly, when memory cells are erased, it is desirable to control the memory cells so that they are not excessively erased at 0 V or less.